Since the beginning of the integrated circuit era, the minimum device dimension has been scaled down for fabrication of highly complex integrated circuits, and, for this reason, a component field effect transistor incorporated in a very large-scale integration has a minimum device dimension which shrinks into the submicron region. However, the shrinkage in the gate length results in that the short-channel effects tend to take place in the field effect transistor. In general, shallow source and drain regions are conducive to suppression of the short-channel effects, so that various attempts are made for controlling the depth of the source and drain regions. One of the attempts is disclosed in "Formation of Shallow Junction by Ion Implantation", Semiconductor World 1986.2, pages 57 to 65. The paper entitled as "Formation of Shallow Junction by Ion Implantation " proposes that impurity atoms should be implanted through a silicon oxide film or, alternatively, through an amorphous silicon film. The paper also proposes a low energy ion implantation. For example, when n= type shallow source and drain regions 1 and 2 are formed in a p-type silicon substrate 3 during a fabrication process of a MIS-type ( metal insulator semiconductor ) field effect transistor shown in FIG. 1, n-type impurity atoms are implanted into the p-type silicon substrate 3 through a silicon oxide film or an amorphous silicon film ( not shown ) previously applied on the major surface of the p-type silicon substrate 3 using a gate electrode 4 as a mask. After formation of the shallow source and drain regions 1 and 2, an insulating film 5 is deposited on the entire surface of the structure, and, then, contact windows are formed in the insulating film 5 to expose the source and drain regions 1 and 2. On the insulating film 5 is deposited aluminum or an aluminum-silicon alloy which is patterned to form metal wiring layers 6 and 7 connected at one ends thereof to the source and drain regions 1 and 2, respectively.
However, a problem is encountered in the prior-art MIS-type field effect transistor in that an irregularity takes place in the profiles of the source and drain regions 1 and 2 because the silicon oxide film or the amorphous silicon film is varied in thickness. Undesirable ion channelings are increased during the ion-implantation. These deteriorate the reliability of the MIS-type field effect transistor and, accordingly, result in reduction in production yield. Moreover, the shallow source and drain regions 1 and 2 are causative of other drawbacks. Namely, resistance thereof are increased, limitations are set to temperatures and time durations of heat-treatments carried out after formation of the source and drain regions 1 and 2, and aluminum spikes should be taken into account upon selection of material.